1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to configurations provided for testing a memory cell.
2. Description of the Background Art
As a conventional test conducted on a semiconductor memory device, a disturb test is conducted to estimate memory leakage.
The disturb test is conducted in various manners and in one such disturb test any single word line in a subarray is turned on/off to conduct the test. Hereinafter, the test employing turning on/off a single word line in a subarray will be referred to as an end page read refresh.
In the end page read refresh, a word line is turned on/off to allow a bit line to have a potential with an amplitude interfering with a memory cell connected to the bit line (the word line to which the memory cell is connected is placed in the inactive state). The bit line""s potential amplitude allows the word line to slightly float to detect a channel leak.
In addition to the above effect, the memory cell""s data (for example of logical high) and the connected bit line""s potential (for example of logical low) are opposite in phase. As such in a memory cell transistor having a processing defect a channel leak can readily occur.
Thus, the end page read refresh only requires a single word line to be turned on/off in a subarray and can thus be conducted in a shorter period of time than a normal disturb test.
If in a semiconductor memory device having a redundant configuration the end page read refresh turns on/off a word line corresponding to a defective word line, rather than the defective word line is not turned on/off and a spare word line is instead turned on/off.
The redundant configuration divided in two types, i.e., a configuration substituting a defective word line in a subarray with a spare word line in the same subarray and a configuration substituting a defective word line in a subarray with a spare word line in a different subarray. The latter configuration is referred to as flexible redundancy.
In the flexible redundancy configuration, however, it is possible that rather than a defective word line a spare word line is turned on/off that exists in a subarray different from the subarray including the defective word line.
As such, it is possible in the flexible redundancy configuration that a channel leak is not detected in a subarray including a defective word line.
The present invention therefore contemplates a semiconductor memory device capable of reliably testing a memory whether or not it has a redundant configuration.
The present invention in one aspect provides a semiconductor memory device including: a memory cell array portion including a plurality of memory cells arranged in rows and columns, a plurality of normal word lines provided corresponding to a plurality of rows, a plurality of bit lines provided corresponding to a plurality of columns, and a spare word line provided for substituting for a defective normal word line of the plurality of normal word lines; a test circuit including a dummy word line and a drive circuit operating to amplify a voltage level of the plurality of bit lines depending on the dummy word line; a decision circuit referring to an address input, to determine whether or not to substitute a selected normal word line with the spare word line; and a select diive circuit operating in a test mode to selectively drive the dummy word line rather than the plurality of normal word lines and the spare word line, and operating in a mode other than the test mode to refer to a decision of the decision circuit to selectively drive a corresponding normal word line or a corresponding spare word line.
Preferably the drive circuit includes a plurality of transistors arranged for the plurality of bit lines, respectively, the plurality of transistors each responding to a potential of the dummy word line by driving a corresponding bit line to a predetermined potential.
In particular, the predetermined potential is determined depending on data written to a memory cell and the plurality of transistors drive their respective bit lines to either one of a ground potential and a power supply potential.
Preferably the semiconductor memory device further includes a dummy formation region formed at an outermost periphery of a region provided with the memory cell array portion, wherein the test circuit is provided in the dummy formation region.
Preferably the semiconductor memory device further includes a dummy formation region provided at an outermost periphery of a region provided with the memory cell array portion, wherein the plurality of transistors are provided in the dummy formation region.
Preferably the plurality of normal word lines are divided into a plurality of array blocks and there are provided more than one spare word line, and in a mode other than the test mode the defective normal word line in each of the plurality of array blocks is substituted by any one of more than one spare word line arranged in a spare block formed in a region different than the plurality of array blocks. In particular the drive circuit is arranged only in the plurality of array blocks.
Preferably there are provided more than one spare word line, the plurality of memory cells, the plurality of normal word lines and more than one spare word line are divided in a plurality of array blocks and the defective normal word line in each of the plurality of array blocks is substituted by a spare word line existing in the same array block.
Preferably the semiconductor memory device further includes a test mode setting circuit operable to set the test mode, wherein the select drive circuit operates to allow the plurality of transistors to be each operable only in the test mode.
Thus the semiconductor memory device can be provided with a test circuit including a dummy word line selected in the end page read refresh mode in place of a normal word line and a spare word line and a drive circuit operable to amplify a level in voltage of a bit line depending on the dummy word line, to ensure that in the test a channel leak is detected.
In particular, the drive circuit can be configured of a transistor. Furthermore the transistor can drive a bit line to a potential allowing a channel leak to be detected, such as a ground potential, a power supply potential and the like.
Furthermore, the dummy word line and the transistor can be formed in a dummy formation region located at an outermost periphery of a region provided with an array block. As such a chip area can be reduced.
Furthermore, even if a semiconductor memory device has a flexible redundancy configuration, a dummy word line can be selected whether or not substitution has been provided. Thus the memory can be tested reliably.
In particular, if a semiconductor memory device has a flexible redundancy configuration a dummy word line is not provided in a block including a spare word line. Thus a chip area can be reduced.
Furthermore, even if a semiconductor memory device has a redundant configuration other than a flexible redundancy configuration the memory can also be tested reliably.
In a mode other than the end page read refresh mode the transistor does not operate. Thus in the mode other than the end page read refresh mode a normal word line or a spare word line can be used in reading/writing data, as conventional.
Furthermore the dummy word line and the transistor can be formed in a dummy formation region positioned in an outermost periphery of a region in which the array block. Thus a chip area can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.